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56Gb/s PAM4 CDR/Retimer, Bi-Di

Package Information

CAD Model: View CAD Model
Pkg. Type: FCCSP
Pkg. Code: AVG54
Lead Count (#): 54
Pkg. Dimensions (mm): 4.8 x 2.8 x 1.0
Pitch (mm): 0.4

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US)
HTS (US)

Product Attributes

Pkg. Type FCCSP
Carrier Type Tray
Application 56G Ethernet SR, 56G Ethernet LR, SFP56
Channels (#) 1
Data Rate Max (Gbps) 56
Function CDR / Retimer
Lead Count (#) 54
Length (mm) 4.8
MOQ 200
Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Pitch (mm) 0.4
Pkg. Dimensions (mm) 4.8 x 2.8 x 1.0
Published No
Qty. per Carrier (#) 490
Qty. per Reel (#) 0
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Temp. Range (°C) -40 to 85°C
Thickness (mm) 1
Width (mm) 2.8

Description

The HXC44200 is a bi-directional dual channel PAM-4 CDR/Retimer. It supports a transmission data rate of 56Gbps PAM4 and 28Gbps NRZ. The HXC44200 can be used in a 50G SFP56 form factor and other small form factor modules. The device is optimized for Ethernet application. It is in full compliance with OIF CEI-56G-VSR and CEI-56G-MR. The total power consumption of the HXC44200 is below 700mW.

The HXC44200 has built-in programmable and adaptive equalization in both the receiver and the transmitter paths to compensate for transmission line losses and inter-symbol interference.

Auto DC-offset calibration is implemented with auto phase calibration and the unique CDR / Retimer architecture enables independent receive and transmit CDR loop bandwidth optimization for increased Jitter Tolerance and reduced Jitter Transfer performance.

The chip has a built-in, single 14GHz master VCO providing the oscillator output for each channel. In addition, the self-test functions, such as a PRBS generator / checker, Jitter Tolerance, and Eye Open Monitor, provide designers and users with module-level diagnostics and function tests.

The HXC44200 also integrates a CPU for programmable control, which could reduce BOM cost and enable better module design. I2C interface is used to control the built-in CPU.