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3.3V Phase-Lock Loop Clock Driver Zero Delay Buffer

Package Information

CAD Model: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG24
Lead Count (#): 24
Pkg. Dimensions (mm): 7.8 x 4.4 x 1.0
Pitch (mm): 0.65

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090
Moisture Sensitivity Level (MSL) 1

Product Attributes

Pkg. Type TSSOP
Lead Count (#) 24
Pb (Lead) Free Yes
Carrier Type Tube
Core Voltage (V) 3.3
Input Freq (MHz) 50 - 175
Input Type LVCMOS
Inputs (#) 1
Length (mm) 7.8
MOQ 558
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 1
Output Freq Range (MHz) 50 - 181
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 10
Package Area (mm²) 34.3
Pb Free Category e3 Sn
Pitch (mm) 0.65
Pkg. Dimensions (mm) 7.8 x 4.4 x 1.0
Published No
Qty. per Carrier (#) 62
Qty. per Reel (#) 0
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Temp. Range (°C) 0 to 70°C
Thickness (mm) 1
Width (mm) 4.4

Description

3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer.  With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions.