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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

20-Output DB2000Q PCIe Clock Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)72
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Assembly LocationTAIWAN
Wafer Fab LocationTAIWAN
Accepts Spread Spec InputYes
Advanced FeaturesMultiple SMBus addresses
App Jitter Compliance25G EDR, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, DB2000Q, QPI, UPI
ArchitectureCommon, SRIS, SRNS
C-C Jitter Max P-P (ps)50
Chipset ManufacturerIntel
Clock Spec.DB2000Q
Core Voltage (V)3.3V
Diff. Input SignalingHCSL
Diff. Inputs1
Diff. Output SignalingLP-HCSL
Diff. Outputs20
Diff. Termination Resistors24
Feedback InputNo
FunctionFanout Buffer
Input Freq (MHz)1 - 400
Input TypeHCSL
Inputs (#)1
Length (mm)10
MOQ2500
Output Banks (#)1
Output Enable (OE) Pins8
Output Freq Range (MHz)1 - 400
Output Impedance85
Output Skew (ps)50
Output TypeLP-HCSL
Output Voltage (V)0.7V
Outputs (#)20
PLLNo
Package Area (mm²)81
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeVFQFPN
Power Consumption Typ (mW)594
Product CategoryPCI Express Clocks, Processor Clock Buffers, Zero Delay Buffers
Reel Size (in)13
Reference OutputNo
Spread SpectrumYes
Supply Voltage (V)3.3 - 3.3
Tape & ReelYes
Thickness (mm)1
Width (mm)10

Description

The 9QXL2000B is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen 4 and Gen 5. It offers integrated terminations for 85Ω transmission lines with individual output impedance trim and via SMBus registers.