Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | LGA |
| Pkg. Code: | LW0064AA |
| Lead Count (#): | 64 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.66 |
| Pitch (mm): | 0.5 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
| Pkg. Type | LGA |
| Lead Count (#) | 64 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 105°C |
| Assembly Location | TAIWAN |
| Wafer Fab Location | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Jitter | 4fs |
| Additive Phase Jitter Typ RMS (fs) | 2.8 |
| Advanced Features | Multiple SMBus addresses, Power Down Tolerant, Flexible Startup Sequencing, SMBus enabled Automatic Clock Parking |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7, DB1206, DB2000Q, QPI, UPI |
| Architecture | Common, SRIS, SRNS |
| Chipset Manufacturer | Intel |
| Clock Spec. | DB2000Q |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 12 |
| Function | Fanout Buffer |
| Input Freq (MHz) | 1 - 400 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| MOQ | 490 |
| Output Banks (#) | 1 |
| Output Enable (OE) Pins | 12 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Outputs (#) | 12 |
| PLL | No |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.66 |
| Power Consumption Typ (mW) | 441 |
| Product Category | Clock Buffers & Drivers, PCI Express Clocks |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.66 |
| VOUT Amplitude Control | No |
| VOUT Slew-rate Control | Yes |
| Width (mm) | 5 |
The 9QXL1200 is an ultra-high performance PCIe Gen7 fanout buffer that is backward compatible with earlier PCIe generations. It features a loss-of-signal (LOS) output for system monitoring and resiliency. The device also incorporates power-down tolerant (PDT) and flexible startup sequencing (FSS) capabilities, simplifying system design.