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DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:SSOP
Pkg. Code:PYG28
Lead Count (#):28
Pkg. Dimensions (mm):10.2 x 5.3 x 1.73
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)28
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)1500
Qty. per Carrier (#)0
Package Area (mm²)54.1
Pkg. Dimensions (mm)10.2 x 5.3 x 1.73
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Accepts Spread Spec InputYes
Advanced FeaturesAccepts Spread Spec Input, Reference Output
App Jitter ComplianceDDR, DDR2
C-C Jitter Max P-P (ps)50
Core Voltage (V)1.8V, 2.5V
Delay ModeVariable
Die FormNo
Diff. Input SignalingSSTL-2
Diff. Output SignalingSSTL-2
Input Freq (MHz)125
Input TypeLVCMOS
Inputs (#)4
Length (mm)10.2
MOQ1500
Output Banks (#)1
Output Freq Range (MHz)125
Output Skew (ps)40
Output TypeSSTL-2
Output Voltage (V)2.5V, 1.8V
Outputs (#)6
Period Jitter Max P-P (ps)30
Pitch (mm)0.65
Pkg. TypeSSOP
PublishedNo
Reel Size (in)13
Reference OutputYes
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelYes
Thickness (mm)1.73
Width (mm)5.3

Description

DDR I/DDR II Phase Lock Loop Zero Delay Buffer