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DB1200GS Frequency Gearing Clock

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PAG56
Lead Count (#):56
Pkg. Dimensions (mm):14.0 x 6.1 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)56
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)34
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Accepts Spread Spec InputYes
Advanced FeaturesHiBW frequency translation capability
App Jitter CompliancePCIe Gen1, PCIe Gen2, FBD
Chipset ManufacturerIntel
Clock Spec.DB1200GS
Diff. Input SignalingHCSL
Diff. Inputs1
Diff. Output SignalingHCSL
Diff. Outputs12
Diff. Termination Resistors48
FunctionBuffer
Length (mm)14
MOQ136
Output Enable (OE) Pins11
Output Freq Range (MHz)400
Package Area (mm²)85.4
Pitch (mm)0.5
Pkg. Dimensions (mm)14.0 x 6.1 x 1.0
Pkg. TypeTSSOP
Power Consumption Typ (mW)970
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)3.3 - 3.3
Tape & ReelNo
Thickness (mm)1
Width (mm)6.1

Description

9FG1200-1 follows the Intel DB1200GS Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the . The can provide outputs up to 400MHz.