Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 9.7 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 28 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 50 |
| C-C Jitter Typ P-P (ps) | 10 |
| Input Freq (MHz) | 100 |
| Output Voltage (V) | 3.3 |
| Package Area (mm²) | 42.7 |
| Pkg. Dimensions (mm) | 9.7 x 4.4 x 1.0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Assembly Location | TAIWAN |
| Wafer Fab Location | SINGAPORE |
| Accepts Spread Spec Input | Yes |
| Advanced Features | HW PLL mode control |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 6 |
| Diff. Termination Resistors | 24 |
| Feedback Input | No |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 9.7 |
| MOQ | 150 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 10 - 110 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Outputs (#) | 6 |
| PLL | Yes |
| Phase Jitter Max RMS (ps) | 1 |
| Phase Jitter Typ RMS (ps) | 0.5 |
| Pitch (mm) | 0.65 |
| Pkg. Type | TSSOP |
| Power Consumption Typ (mW) | 442 |
| Product Category | PCI Express Clocks |
| Prog. Clock | No |
| Prog. Interface | SMBUS |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
Resources for 9DB633
Description
The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.