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9DB436

Obsolete

4-Output 3.3V HCSL PCIe Buffer

Features

  • Four 0.7V current-mode differential HCSL output pairs
  • PCIe Gen 3 jitter < 0.6ps RMS in ZDB mode
  • PCIe Gen 4 additive jitter < 0.1ps RMS in fanout mode
  • SPS internal receiver bias network keeps the input clock parked when input is floating
  • Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
  • OE# pins default to controlling outputs
  • Supports zero delay buffer mode and fanout mode
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible
  • Three selectable SMBus addresses
Find Other Products in Application-Specific Clocks
9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram
9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram

Description

The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen 1–3 in zero delay mode and PCIe Gen 1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.

Applications

  • Riser cards
  • Storage
  • Networking
  • JBOD

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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