Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SSOP |
| Pkg. Code: | PYG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 10.2 x 5.3 x 1.73 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 28 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 1500 |
| Qty. per Carrier (#) | 0 |
| Chipset Name | DB400 |
| Input Freq (MHz) | 200 |
| Output Voltage (V) | 3.3 |
| Package Area (mm²) | 54.1 |
| Pkg. Dimensions (mm) | 10.2 x 5.3 x 1.73 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Accepts Spread Spec Input | Yes |
| Advanced Features | HW PLL mode control |
| App Jitter Compliance | PCIe Gen1 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 4 |
| Diff. Termination Resistors | 16 |
| Feedback Input | No |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 10.2 |
| MOQ | 1500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 10 - 400 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Outputs (#) | 4 |
| PLL | Yes |
| Pitch (mm) | 0.65 |
| Pkg. Type | SSOP |
| Power Consumption Typ (mW) | 300 |
| Prog. Clock | No |
| Prog. Interface | SMBUS |
| Published | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 1.73 |
| Width (mm) | 5.3 |
Resources for 9DB401
Description
The 9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the 952601, 954101 or 954201. It provides outputs meeting tight cycle-to-cycle jitter (50 ps) and output-to-output skew (50ps) requirements.