Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PAG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 12.5 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Pkg. Type | TSSOP |
| Lead Count (#) | 48 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| Accepts Spread Spec Input | Yes |
| Advanced Features | HW PLL mode control |
| Architecture | Common,Data,Separate,Separate w/Spread |
| C-C Jitter Max P-P (ps) | 50 |
| Chipset Manufacturer | Intel |
| Chipset Name | DB800v2 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 8 |
| Diff. Termination Resistors | 32 |
| Feedback Input | No |
| Input Freq (MHz) | 100 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 12.5 |
| MOQ | 2000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 80 - 220 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 8 |
| PLL | Yes |
| Package Area (mm²) | 76.3 |
| Pb Free Category | e3 Sn |
| Phase Jitter Max RMS (ps) | 0.1 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 12.5 x 6.1 x 1.0 |
| Power Consumption Typ (mW) | 531 |
| Prog. Clock | Yes |
| Prog. Interface | SMBUS |
| Published | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2000 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
Resources for 9DB108
Description
The 9DB108 8-output differential buffer for PCIe Gen 1 is not recommended for new designs. The 9DB803 8-output differential buffer for PCIe Gen 2 is the recommended replacement.