Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | QSOP |
| Pkg. Code: | PCG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 8.7 x 3.8 x 1.47 |
| Pitch (mm): | 0.64 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Carrier (#) | 55 |
| Package Area (mm²) | 33.1 |
| Pitch (mm) | 0.64 |
| Pkg. Dimensions (mm) | 8.7 x 3.8 x 1.47 |
| Qty. per Reel (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Accepts Spread Spec Input | Yes |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 35 |
| C-C Jitter Typ P-P (ps) | 30 |
| Chipset Name | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle, San Clemente, Seaburg, Tylersburg |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 2 |
| Diff. Termination Resistors | 8 |
| Feedback Input | No |
| Function | Zero Delay Buffer |
| Input Freq (MHz) | 50 - 100 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 8.7 |
| MOQ | 220 |
| Multiplication Value | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 99 - 101 |
| Output Skew (ps) | 25 |
| Output Type | HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 2 |
| PLL | Yes |
| Pkg. Type | QSOP |
| Platform Name | Bensley, Caneland, Glidewell, Lindenhurst, Truland, Stoakley, Thurley, Cranberry Lake |
| Power Consumption Typ (mW) | 247 |
| Prog. Clock | No |
| Published | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1.47 |
| Width (mm) | 3.8 |
Resources for 9DB102
Description
The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.