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Programmable Timing Control Hub™ for Next Gen P4™ processor

Package Information

CAD Model: View CAD Model
Pkg. Type: SSOP
Pkg. Code: PVG48
Lead Count (#): 48
Pkg. Dimensions (mm): 15.9 x 7.5 x 2.3
Pitch (mm): 0.64

Environmental & Export Classifications

Pb (Lead) Free Yes
Moisture Sensitivity Level (MSL) 1
ECCN (US)
HTS (US)

Product Attributes

Pkg. Type SSOP
Lead Count (#) 48
Pb (Lead) Free Yes
Carrier Type Tube
C-C Jitter Max P-P (ps) 125
Chipset Manufacturer VIA
Core Voltage (V) 3.3
Die Form No
Diff. Output Signaling HCSL
Function Clock Generator
Input Freq (MHz) 14.318 - 400
Length (mm) 15.9
MOQ 240
Moisture Sensitivity Level (MSL) 1
Output Freq Range (MHz) 14.318 - 400
Output Voltage (V) 2.5V, 3.3V
Package Area (mm²) 119.3
Pb Free Category e3 Sn
Pitch (mm) 0.64
Pkg. Dimensions (mm) 15.9 x 7.5 x 2.3
Published No
Qty. per Carrier (#) 30
Qty. per Reel (#) 0
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Supply Voltage (V) 2.5 - 2.5, 3.3 - 3.3
Tape & Reel No
Temp. Range (°C) 0 to 70°C
Thickness (mm) 2.3
Width (mm) 7.5
Xtal Freq (MHz) 14.3182 - 14.3182
Xtal Inputs (#) 1

Description

IDT952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such
as the 93788, it provides all the necessary clock signals for such a system.
The IDT952906A is part of a whole new line of IDT clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates IDT's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.