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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

DDR Phase Lock Loop Clock Driver

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG28
Lead Count (#):28
Pkg. Dimensions (mm):9.7 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)1

Product Attributes

Pkg. TypeTSSOP
Lead Count (#)28
Pb (Lead) FreeYes
Carrier TypeReel
Length (mm)9.7
MOQ2000
Moisture Sensitivity Level (MSL)1
Package Area (mm²)42.7
Pb Free Categorye3 Sn
Pitch (mm)0.65
Pkg. Dimensions (mm)9.7 x 4.4 x 1.0
Qty. per Carrier (#)0
Qty. per Reel (#)2000
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Temp. Range (°C)0 to 70°C
Thickness (mm)1
Width (mm)4.4

Description

2.5V 1 to 4 differential clock distributor. Optimized for clock distribution in DDR SDRAM applications.  Operating frequency: 60MHZ to 220MHz