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Direct Rambus™ Clock Generator

Package Information

CAD Model: View CAD Model
Pkg. Type: QSOP
Pkg. Code: PCG24
Lead Count (#): 24
Pkg. Dimensions (mm): 8.7 x 3.8 x 1.47
Pitch (mm): 0.64

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090
Moisture Sensitivity Level (MSL) 1

Product Attributes

Pkg. Type QSOP
Lead Count (#) 24
Pb (Lead) Free Yes
Carrier Type Tube
C-C Jitter Max P-P (ps) 40
Chipset Manufacturer RAMBUS
Clock Spec. DRCG
Core Voltage (V) 3.3
Feedback Input No
Function Buffer
Input Freq (MHz) 50 - 50, 66.66 - 66.66
Input Type LVCMOS
Inputs (#) 1
Length (mm) 8.7
MOQ 220
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 1
Output Freq Range (MHz) 600
Output Voltage (V) 3.3
Outputs (#) 1
Package Area (mm²) 33.1
Pb Free Category e3 Sn
Pitch (mm) 0.64
Pkg. Dimensions (mm) 8.7 x 3.8 x 1.47
Prog. Clock No
Published No
Qty. per Carrier (#) 55
Qty. per Reel (#) 0
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Tape & Reel No
Temp. Range (°C) 0 to 70°C
Thickness (mm) 1.47
Width (mm) 3.8

Description

The 9212-13 is a High-speed clock generator providing up to 600 MHz differential clock source for direct Rambus™ memory system. It includes DDLL (Distributed Delay locked loop) and phase detection mechanism to synchronize the direct Rambus™ channel clock to an external system clock. 9212-13 provides a solution for a broad range of Direct Rambus memory applications. The device works in conjunction with the 9250-09. The 9212-13 power management support system turns "off" the Rambus™ channel clock to minimize power consumption for mobile and other power–sensitive applications. In "clock off" mode the device remains "on" while the output is disabled, allowing fast transitions between clock-off and clock–on states. In "power down" mode it completely powers down for minimum power dissipation. The 9212-13 meets the requirements for input frequency tracking when the input frequency clock is using Spread Spectrum clocking and also the optimum bandwidth is maintained while attenuating the jitter of the reference signal.