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JESD204B/C Clock Jitter Attenuator

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG88
Lead Count (#):88
Pkg. Dimensions (mm):10.0 x 10.0 x 0.9
Pitch (mm):0.4

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)88
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)168
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Country of AssemblyTAIWAN, CHINA
Country of Wafer FabricationSINGAPORE, UNITED STATES
Accepts Spread Spec InputNo
Additive Phase Jitter Typ RMS (fs)63.1
Additive Phase Jitter Typ RMS (ps)0.063
Adjustable PhaseYes
Advanced FeaturesHoldover, Phase Delay, Input Switching, JESD204B, Programmable Clock
Channels (#)1
Core Voltage (V)3.3V
DPLL Channels (#)0
Feedback Divider Resolution (bits)12
Fractional Output Dividers (#)0
Frequency Plan2949.12 / Output_Divider
Input Freq (MHz)1.92 - 2000
Input RedundancyInput Monitor, Auto-switch, Manual switch, Revertive and non-revertive switch, Holdover
Input Ref. Divider Resolution (bits)12
Input TypeLVDS, LVPECL
Inputs (#)2
JESD204B/C CompliantYes
Length (mm)10
Loop Bandwidth Range (Hz)20 - 100
MOQ168
Noise Floor (dBc/Hz)-160
Output Banks (#)5
Output Divider Resolution (bits)8
Output Freq Range (MHz)18.432 - 2949.12
Output TypeLVDS, LVPECL
Output Voltage (V)3.3V
Outputs (#)15
PLLYes
Package Area (mm²)64
Phase Jitter Typ RMS (fs)63.1
Phase Jitter Typ RMS (ps)0.063
Phase Noise Supports GSMYes
Pitch (mm)0.4
Pkg. Dimensions (mm)10.0 x 10.0 x 0.9
Pkg. TypeVFQFPN
Ports (#)1
Price (USD)$14.41766
Product CategoryJESD204B/C
Prog. ClockYes
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)3.3 - 3.3
Synthesis ModeInteger
Tape & ReelNo
Thickness (mm)0.9
Width (mm)10
Xtal Freq (KHz)30720 - 250000

Description

The 8V19N492 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.

A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.

The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The 8V19N492 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT.

For information regarding evaluation boards and material, please contact your local sales representative.