Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | CABGA |
| Pkg. Code: | BDG100 |
| Lead Count (#): | 100 |
| Pkg. Dimensions (mm): | 11.0 x 11.0 x 1.2 |
| Pitch (mm): | 1 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 100 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e1 SnAgCu |
| Temp. Range (°C) | -40 to 85°C |
| Adjustable Phase | Yes |
| Advanced Features | Holdover, Phase Delay, Input Switching |
| Channels (#) | 1 |
| Core Voltage (V) | 3.3 |
| Feedback Divider Resolution (bits) | 15 |
| Fractional Output Dividers (#) | 1 |
| Frequency Plan | 2500 / Output_Divider, 2400 / Output_Divider |
| Input Freq (MHz) | 0.008 - 250 |
| Input Redundancy | Input Monitor, Auto-switch, Manual switch |
| Input Ref. Divider Resolution (bits) | 15 |
| Input Type | LVDS, LVPECL |
| Inputs (#) | 2 |
| JESD204B/C Compliant | No |
| Length (mm) | 11 |
| MOQ | 168 |
| Noise Floor (dBc/Hz) | -150 |
| Output Banks (#) | 5 |
| Output Divider Resolution (bits) | 8 |
| Output Freq Range (MHz) | 15.625 - 2500 |
| Output Skew (ps) | 50 |
| Output Type | LVDS, LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 18 |
| Package Area (mm²) | 64 |
| Phase Jitter Typ RMS (fs) | 75 |
| Phase Jitter Typ RMS (ps) | 0.075 |
| Phase Noise Supports GSM | Yes |
| Pitch (mm) | 1 |
| Pkg. Dimensions (mm) | 11.0 x 11.0 x 1.2 |
| Pkg. Type | CABGA |
| Prog. Clock | Yes |
| Published | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 3.3 - 3.3 |
| Synthesis Mode | Integer, Fractional |
| Tape & Reel | No |
| Thickness (mm) | 1.2 |
| Width (mm) | 11 |
Resources for 8V19N478
Description
The 8V19N478 is a fully integrated FemtoClock™ NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of 10/40/100/400 Gigabit-Ethernet line cards. The device is optimized to deliver excellent phase noise performance as required to drive physical layer devices, and provides the clean clock frequencies of 625MHz, 500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator, and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal, and synthesizes the target frequency. This PLL has a VCO circuit at 2500MHz. The 8V19N478 generates the output clock signals from the VCO by frequency division. Four independent frequency dividers are available; three support integer-divider ratios, and one integer as well as fractional-divider ratios. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through an I²C interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications.
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