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Renesas Electronics Corporation
FemtoClock NG Jitter Attenuator and Clock Synthesizer

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)72
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)168
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Adjustable PhaseYes
Advanced FeaturesJESD204B, Holdover, Phase Delay, Programmable Clock
Core Voltage (V)3.3
Feedback Divider Resolution (bits)15
Fractional Output Dividers (#)0
Frequency Plan1920 / Output_Divider, 1966.08 / Output_Divider
Input Freq (MHz)0.01 - 250
Input RedundancyClock Monitor, Holdover
Input Ref. Divider Resolution (bits)8
Input TypeLVPECL, LVDS
Inputs (#)1
JESD204B/C CompliantYes
Length (mm)10
Loop Bandwidth Range (Hz)30 - 30
MOQ168
Noise Floor (dBc/Hz)-161.8
Output Banks (#)3
Output Divider Resolution (bits)5
Output Freq Range (MHz)19.792 - 2000
Output Skew (ps)65
Output TypeLVDS, LVPECL
Output Voltage (V)3.3
Outputs (#)10
Package Area (mm²)100
Phase Jitter Typ RMS (fs)91.4
Phase Jitter Typ RMS (ps)0.091
Phase Noise Supports GSMYes
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeVFQFPN
Product CategoryJESD204B/C, Jitter Attenuators
Prog. ClockYes
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)3.3 - 3.3
Synthesis ModeInteger
Tape & ReelNo
Thickness (mm)1
Width (mm)10
Xtal Freq (KHz)25 - 250

Description

The 8V19N407Z-19 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer. The device is a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards and is optimized to deliver excellent phase noise performance. The device supports JESD204B subclass 0 and 1 clock implementations. The device is very flexible in programming the output frequency and phase. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The first stage PLL lock on the VCXO-PLL output signal and synthesizes the target frequency. The second stage PLL uses an internal VCO.

The device supports the clock generation of high-frequency clocks from the VCO and low-frequency system reference signals (SYSREF). The system reference signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The input is monitored for activity. The "hold-over" is provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a 4-wire SP serial interface and reports lock and signal loss status in internal registers and optionally via a lock detect (nINT) output. The device is packaged in a lead-free (RoHS 6) 72-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication, and networking end equipment requirements.