Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 8.0 x 8.0 x 0.85 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 56 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 260 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Additive Phase Jitter Typ RMS (fs) | 300 |
| Advanced Features | Programmable Clock, Feedback Input |
| Core Voltage (V) | 3.3V, 2.5V |
| Feedback Input | Yes |
| Input Freq (MHz) | 10 - 120 |
| Input Type | Crystal, Differential |
| Inputs (#) | 2 |
| Length (mm) | 8 |
| MOQ | 260 |
| Output Banks (#) | 5 |
| Output Freq Range (MHz) | 8.33 - 125 |
| Output Type | LVPECL, LVDS, LVCMOS |
| Output Voltage (V) | 3.3V, 2.5V |
| Outputs (#) | 13 |
| Package Area (mm²) | 64 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 8.0 x 8.0 x 0.85 |
| Pkg. Type | VFQFPN |
| Product Category | Ultra-Low Jitter Clocks (<300 fs RMS) |
| Prog. Clock | Yes |
| Prog. Interface | Serial |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Thickness (mm) | 0.85 |
| Width (mm) | 8 |
Resources for 8T49N4811
Description
The 8T49N4811 is a highly flexible FemtoClock® NG pin-programmable clock generator suitable for networking and communications applications. It can generate five different output frequencies with multiple copies of each. A fundamental mode crystal, single-ended, or differential input reference may be used as the source for the output frequency.
The use of pin programming to select the input source/frequency, desired output frequencies, and output styles allows a single device to be used in a wide variety of applications without the need for register programming.
Selection pins use 3-level options to maximize flexibility while minimizing package size. Selection is performed by tying a selection pin high or low or by leaving it floating, eliminating the need for passive components to drive a desired logic level.