Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG40 |
| Lead Count (#): | 40 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 40 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Programmable Clock |
| C-C Jitter Max P-P (ps) | 40 |
| Core Voltage (V) | 3.3V, 2.5V |
| Divider Value | 2 |
| Family Name | UFT |
| Feedback Divider | 1 - 255 |
| Feedback Input | No |
| Input Freq (MHz) | 0.008 - 710 |
| Input Type | Crystal, HCSL, LVHSTL, LVDS, LVPECL |
| Inputs (#) | 2 |
| Length (mm) | 6 |
| MOQ | 490 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 0.98 - 1300 |
| Output Signaling | LVPECL, LVDS |
| Output Skew (ps) | 35 |
| Output Type | LVPECL, LVDS |
| Output Voltage (V) | 3.3V, 2.5V |
| Outputs (#) | 2 |
| Package Area (mm²) | 36 |
| Period Jitter Max P-P (ps) | 8.7 |
| Period Jitter Typ P-P (ps) | 5.1 |
| Phase Jitter Max RMS (ps) | 0.65 |
| Phase Jitter Typ RMS (fs) | 378 |
| Phase Jitter Typ RMS (ps) | 0.378 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Published | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| VCO Max Freq (MHz) | 2600 |
| VCO Min Freq (MHz) | 1995 |
| Width (mm) | 6 |
| Xtal Freq (KHz) | 16 - 40 |
| Xtal Inputs (#) | 1 |
Resources for 8T49N205I
Description
The 8T49N205I is a highly flexible FemtoClock® NG general-purpose, low phase noise frequency translator/synthesizer with Phase Build-Out (PBO) suitable for networking and communications applications. It can generate any output frequency in the 0.98MHz to 312.5MHz range and most output frequencies in the 312.5MHz to 1,300MHz range. A wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the source for the output frequency.
This device provides two factory-programmed default power-up configurations burned into One-Time Programmable (OTP) memory. The configuration to be used is selected by the CONFIG pin. The two configurations are specified by the customer and are programmed by Renesas during the final test phase from an on-hand stock of blank devices. The two configurations may be completely independent of one another. One usage example might be to install the device on a line card with two optional daughter cards: an OC-12 option requiring a 622.08MHz LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet option requiring a 125MHz LVPECL clock translated from the same 19.44MHz input reference.
To implement other configurations, these power-up default settings can be overwritten after power-up using the I2C interface and the device can be completely reconfigured. However, these settings would have to be rewritten next time the device powers up.
To see other devices in this product family, visit the Universal Frequency Translators page.