Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 32 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | SINGAPORE |
| Additive Phase Jitter Typ RMS (fs) | 37.6 |
| Core Voltage (V) | 3.3V, 2.5V |
| Family Name | 8T39 |
| Function | Buffer |
| Input Freq (MHz) | 1500 |
| Input Type | Crystal, HCSL, LVDS, LVPECL, HSTL, LVCMOS |
| Inputs (#) | 3 |
| Length (mm) | 5 |
| MOQ | 2500 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 1500 |
| Output Skew (ps) | 81 |
| Output Type | HCSL, LVDS, LVPECL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 4 |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Price (USD) | $4.61978 |
| Product Category | Clock Buffers & Drivers |
| Prog. Interface | Pin select |
| Published | No |
| Reel Size (in) | 13 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
Resources for 8T39204
Description
The 8T39204 is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS, or HCSL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.