Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 48 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 260 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | AUSTRIA |
| Additive Phase Jitter Typ RMS (fs) | 43 |
| Additive Phase Jitter Typ RMS (ps) | 0.043 |
| Adjustable Phase | No |
| Advanced Features | Dual Buffer |
| Channels (#) | 2 |
| Core Voltage (V) | 2.5V, 3.3V |
| Family Name | 8SLVP |
| Function | Buffer |
| Input Freq (MHz) | 2000 |
| Input Type | LVPECL |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 260 |
| Noise Floor (dBc/Hz) | -162 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 2000 |
| Output Skew (ps) | 25 |
| Output Type | LVPECL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 16 |
| Package Area (mm²) | 49 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Price (USD) | $7.79694 |
| Published | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 7 |
Resources for 8SLVP2108I
Description
The 8SLVP2108I is a high-performance differential dual 1:8 LVPECL fanout buffer designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVP2108I is characterized for operation from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP2108I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with eight low-skew outputs each are available. The integrated bias voltage references enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.