Skip to main content
Low Skew,÷2,÷4,÷8 Differential-to-LVPECL Clock Divider

Package Information

CAD Model:View CAD Model
Pkg. Type:SOIC
Pkg. Code:DCG16
Lead Count (#):16
Pkg. Dimensions (mm):9.9 x 3.9 x 1.5
Pitch (mm):1.27

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)3
Qty. per Carrier (#)48
Package Area (mm²)38.6
Pitch (mm)1.27
Pkg. Dimensions (mm)9.9 x 3.9 x 1.5
Qty. per Reel (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Adjustable PhaseNo
Channels (#)1
Core Voltage (V)2.5V, 3.3V
Divider Value2, 4, 8
FunctionDivider
Input Freq (MHz)3200
Input TypeCML, LVDS, LVPECL, SSTL
Inputs (#)1
Length (mm)9.9
MOQ2544
Output Banks (#)3
Output Freq Range (MHz)3200, 1600, 800
Output Skew (ps)50
Output TypeLVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)3
Pkg. TypeSOIC
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5, 3.3 - 3.3
Tape & ReelNo
Thickness (mm)1.5
Width (mm)3.9

Description

The 8S73034I is a high-speed, differential-to- LVPECL clock divider designed for high-performance telecommunication, computing and networking applications. High clock frequency capability and the differential design make the 8S73034I an ideal choice for performance clock distribution networks. The device frequency-divides the input clock by ÷2, ÷4 and ÷8. Each frequency-divided clock signal is output at a separate LVPECL output. The differential input pair can be driven by LVPECL, LVDS, CML and SSTL signals. Single-ended input signals are supported by using the integrated bias voltage generator (VBB). The 8S73034I is optimized for 3.3V and 2.5V power supply voltages and the temperature range of -40 to +85°C. The device is available in space-saving 16-lead TSSOP and SOIC packages.