Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 1.0 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 20 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Additive Phase Jitter Typ RMS (fs) | 60 |
| Additive Phase Jitter Typ RMS (ps) | 0.06 |
| Adjustable Phase | No |
| Channels (#) | 1 |
| Core Voltage (V) | 1.8 |
| Divider Value | 1, 2, 4, 8 |
| Function | Buffer, Divider |
| Input Freq (MHz) | 1000 |
| Input Type | LVDS, LVPECL |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| MOQ | 150 |
| Noise Floor (dBc/Hz) | -153 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1000, 500, 250, 125 |
| Output Skew (ps) | 100 |
| Output Type | LVPECL |
| Output Voltage (V) | 1.8 |
| Outputs (#) | 4 |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Published | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4 |
Resources for 8P73S674i
Description
The 8P73S674 is a 1.8V LVPECL clock divider and fanout buffer designed for clock signal division and fanout in wireless base stations (radio and baseband), high-end computing, and telecommunication equipment. The device is optimized to deliver excellent phase noise performance. The 8P73S674 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection. It offers the frequency division by ÷1, ÷2, ÷4, and ÷8. Four low-skew 1.8V LVPECL outputs are available for and support clock output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL outputs are terminated 50Ω to GND. Outputs can be disabled to save power consumption if not used. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication, and networking end equipment requirements.