Skip to main content
2:8 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks

Package Information

CAD Model: View CAD Model
Pkg. Type: VFQFPN
Pkg. Code: NBG28
Lead Count (#): 28
Pkg. Dimensions (mm): 5.0 x 5.0 x 0.8
Pitch (mm): 0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 28
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2500
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Country of Assembly TAIWAN
Country of Wafer Fabrication AUSTRIA, SINGAPORE
Additive Phase Jitter Typ RMS (fs) 41
Additive Phase Jitter Typ RMS (ps) 0.041
Adjustable Phase No
Channels (#) 1
Core Voltage (V) 1.8
Family Name 8P34S
Input Freq (MHz) 1200
Input Type LVPECL, LVDS, CML
Inputs (#) 2
Length (mm) 5
Longevity 2040 Apr
MOQ 2500
Noise Floor (dBc/Hz) -162
Output Banks (#) 1
Output Freq Range (MHz) 1200
Output Skew (ps) 20
Output Type LVDS
Output Voltage (V) 1.8V, 2.5V
Outputs (#) 8
Package Area (mm²) 25
Pitch (mm) 0.5
Pkg. Dimensions (mm) 5.0 x 5.0 x 0.8
Pkg. Type VFQFPN
Price (USD) $6.8735
Published No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Supply Voltage (V) 1.8 - 1.8
Tape & Reel Yes
Thickness (mm) 0.8
Width (mm) 5

Description

The 8P34S1208 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1208 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the differential device input. The device is optimized for low power consumption and low additive phase noise.