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Multi-Channel DPLL/DCO - Eight Channels

Package Information

CAD Model:View CAD Model
Pkg. Type:CABGA
Pkg. Code:AJG144
Lead Count (#):144
Pkg. Dimensions (mm):10.0 x 10.0 x 1.2
Pitch (mm):0.8

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)144
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)168
Pb (Lead) FreeYes
Pb Free Categorye1 SnAgCu
Temp. Range (°C)-40 to 85°C
Country of AssemblyPHILIPPINES
Country of Wafer FabricationSINGAPORE
Channels (#)8
Core Voltage (V)2.5V, 3.3V
Diff. Inputs8
Diff. Outputs12
Family NameClockMatrix
Fractional Output Dividers (#)8
FunctionMulti-channel DPLL / DCO
Input Freq (MHz)0.001 - 1000
Input TypeHCSL, LVDS, LVHSTL, LVPECL, SSTL
Inputs (#)16
Length (mm)10
MOQ168
Output Banks (#)8
Output Freq Range (MHz)5.0E-7 - 1000
Output Skew (ps)50
Output TypeHSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL
Output Voltage (V)1.2V, 1.5V, 1.8V, 2.5V, 3.3V
Outputs (#)24
Phase Jitter Max RMS (ps)0.2
Phase Jitter Typ RMS (ps)0.15
Pitch (mm)0.8
Pkg. Dimensions (mm)10.0 x 10.0 x 1.2
Pkg. TypeCABGA
Price (USD)$36.98179
Product CategoryClock Matrix
Prog. InterfaceI2C, SPI
PublishedNo
Reference OutputNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1.2
Width (mm)10
Xtal Freq (KHz)25 - 54

Description

The 8A34041 multi-channel Digital PLL/Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion, and timing paths for common communications protocols such as Synchronous Ethernet (SyncE), Optical Transport Network (OTN), and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SerDes running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.