Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 6.5 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 74 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| App Jitter Compliance | STM-1 (OC-3/STS-3), STM-4 (OC-12/STS-12) |
| Core Voltage (V) | 3.3 |
| Divider Value | 1, 4 |
| Feedback Divider | 1 - 1 |
| Feedback Input | No |
| Input Freq (MHz) | 19.44 - 19.44 |
| Input Type | LVCMOS, LVDS, LVPECL |
| Inputs (#) | 2 |
| Length (mm) | 6.5 |
| MOQ | 74 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 155.52 - 155.52, 622.08 - 622.08 |
| Output Signaling | LVDS |
| Output Type | LVDS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 28.6 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 6.5 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Prog. Clock | No |
| Published | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| VCO Max Freq (MHz) | 621 |
| VCO Min Freq (MHz) | 622 |
| Width (mm) | 4.4 |
Resources for 894D115I-04
Description
The 894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals. Input and output are differential signals for best signal integrity and to support high clock and data rates. All control inputs and outputs are single-ended signals. An internal PLL is used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a signal detect input and a lock detect output. A bypass circuit is provided to facilitate factory tests.