Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Adjustable Phase | No |
| Advanced Features | Universal outputs |
| Channels (#) | 1 |
| Core Voltage (V) | 2.5V, 3.3V |
| Divider Value | 2, 4, 8, 16 |
| Function | Buffer, Multiplexer, Divider |
| Input Freq (MHz) | 2500 |
| Input Type | CML, LVDS, LVPECL |
| Inputs (#) | 2 |
| Length (mm) | 4 |
| MOQ | 75 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1250, 625, 312.5, 156.25 |
| Output Skew (ps) | 25 |
| Output Type | LVPECL, LVDS |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 2 |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Product Category | Clock Buffers & Drivers, Clock Dividers, Clock Multiplexers, RF Buffers |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 4 |
The 879S216I-02 is a Differential-to-LVPECL/ LVDS Clock Divider which can operate up to 2.5GHz. 879S216I-02 has 2 selectable differential clock inputs. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. 879S216I-02 can divide the input clock by ÷2, ÷4, ÷8 and ÷16. Table 4A lists all the available output dividers.