Package Information
| Pkg. Type: | TQFP |
| Pkg. Code: | PPG52 |
| Lead Count (#): | 52 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.4 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
Product Attributes
| Pkg. Type | TQFP |
| Lead Count (#) | 52 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| Advanced Features | Feedback Input |
| C-C Jitter Typ P-P (ps) | 50 |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 10 - 25 |
| Input Type | Crystal |
| Inputs (#) | 1 |
| Length (mm) | 10 |
| MOQ | 160 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 400 |
| Output Skew (ps) | 250 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 13 |
| Package Area (mm²) | 100 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.4 |
| Prog. Clock | No |
| Published | No |
| Qty. per Carrier (#) | 160 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1.4 |
| Width (mm) | 10 |
Resources for 873990
Description
The 873990 is a low voltage, low skew, 3.3V LVPECL/ ECL Clock Generator. The 873990 has two selectable clock inputs. The XTAL1 and XTAL2 are used to interface to a crystal and the TEST_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates clocks with "zero delay". The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 400MHz and the input frequency range is 6.25MHz to 125MHz. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. The 873990 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other.