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LVCMOS Clock Generator

Package Information

CAD Model: View CAD Model
Pkg. Type: PLCC
Pkg. Code: PLG28
Lead Count (#): 28
Pkg. Dimensions (mm): 11.5 x 11.5 x 3.63
Pitch (mm): 1.27

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 28
Carrier Type Reel
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 500
Qty. per Carrier (#) 0
Package Area (mm²) 132.3
Pitch (mm) 1.27
Pkg. Dimensions (mm) 11.5 x 11.5 x 3.63
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Advanced Features Feedback Input
C-C Jitter Max P-P (ps) 150
Core Voltage (V) 3.3
Feedback Input Yes
Input Freq (MHz) 2.5 - 100
Input Type LVCMOS
Inputs (#) 2
Length (mm) 11.5
MOQ 500
Output Banks (#) 3
Output Freq Range (MHz) 2.5 - 160
Output Skew (ps) 300
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 8
Pkg. Type PLCC
Prog. Clock No
Published No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 3.63
Width (mm) 11.5

Description

The 870919I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Several output configurations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The LOCK output asserts to indicate when phase-lock has been achieved. The 870919I-01 device is a member of the family of high performance clock solutions from IDT.