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Low Skew, ÷1,÷2 Clock Generator

Package Information

CAD Model:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PRG48
Lead Count (#):48
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)48
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Core Voltage (V)2.5V, 3.3V
Divider Value1, 2
Feedback InputNo
FunctionBuffer, Multiplexer
Input Freq (MHz)250
Input TypeLVCMOS
Inputs (#)1
Length (mm)7
MOQ2000
Output Banks (#)4
Output Freq Range (MHz)250
Output Skew (ps)250
Output TypeLVCMOS
Output Voltage (V)2.5V, 3.3V
Outputs (#)20
Package Area (mm²)49
Pitch (mm)0.5
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Pkg. TypeTQFP
Prog. ClockNo
PublishedNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1.4
Width (mm)7

Description

The 8701I is a low skew, ÷1, ÷2 Clock Generator. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The 8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the 8701I ideal for those clock distribution applications demanding well defined performance and repeatability.