Skip to main content
62.5MHz to 250MHz, 1:4 LVCMOS/LVTTL Zero Delay Clock Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG16
Lead Count (#):16
Pkg. Dimensions (mm):5.0 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)16
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)2500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Advanced FeaturesFeedback Input
C-C Jitter Max P-P (ps)45
Core Voltage (V)2.5V, 3.3V
Feedback InputYes
Input Freq (MHz)62.5 - 250
Input TypeLVCMOS
Inputs (#)1
Length (mm)5
MOQ2500
Output Banks (#)1
Output Freq Range (MHz)62.5 - 250
Output Skew (ps)55
Output TypeLVCMOS
Output Voltage (V)2.5V, 3.3V
Outputs (#)4
Package Area (mm²)22
Pitch (mm)0.65
Pkg. Dimensions (mm)5.0 x 4.4 x 1.0
Pkg. TypeTSSOP
Prog. ClockNo
PublishedNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1
Width (mm)4.4

Description

The 86004-01 is a high performance 1-to-4 LVCMOS/LVTTL Clock Buffer and a member of the family of High Performance Clock Solutions from IDT. The 86004-01 has a fully integrated PLL and can be configured as zero delay buffer and has an input and output frequency range of 62.5MHz to 250MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.