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Renesas Electronics Corporation
Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG20
Lead Count (#):20
Pkg. Dimensions (mm):6.5 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)20
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)74
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (ps)0.164
Core Voltage (V)3.3
Diff. Input Signaling3.3
FunctionBuffer
Input Freq (MHz)800
Input TypeLVPECL, LVDS, HSTL, SSTL, LVDS, HCSL, CML
Inputs (#)2
Length (mm)6.5
MOQ74
Multiply/Divide Value1
Output Banks (#)1
Output Freq Range (MHz)650
Output SignalingLVDS
Output Skew (ps)40
Output TypeLVDS
Output Voltage (V)3.3
Outputs (#)4
Package Area (mm²)28.6
Pitch (mm)0.65
Pkg. Dimensions (mm)6.5 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers, Clock Multiplexers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)3.3 - 3.3
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 8543I is a low-skew, high-performance 1-to-4 differential-to-LVDS clock fanout buffer. Utilizing low voltage differential signaling (LVDS) the 8543I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The 8543I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the 8543I ideal for those applications demanding well-defined performance and repeatability.