Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 32 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | MALAYSIA |
| Country of Wafer Fabrication | AUSTRIA |
| Additive Phase Jitter Typ RMS (fs) | 60 |
| Additive Phase Jitter Typ RMS (ps) | 0.06 |
| Adjustable Phase | No |
| Channels (#) | 1 |
| Core Voltage (V) | 2.5V, 3.3V |
| Function | Buffer |
| Input Freq (MHz) | 1500 |
| Input Type | CML, LVPECL, SSTL |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1500 |
| Output Skew (ps) | 50 |
| Output Type | LVPECL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 12 |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Published | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
Resources for 853S12I
Description
The 853S12I is a low skew, 1-to-12 Differential-to- 3.3V, 2.5V LVPECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The PCLK, nPCLK pair accepts LVPECL, CML, and SSTL differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 853S12I ideal for those clock distribution applications demanding well defined performance and repeatability.