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LVPECL Frequency Synthesizer

Package Information

Pkg. Type: SOIC
Pkg. Code: PSG28
Lead Count (#): 28
Pkg. Dimensions (mm): 17.9 x 7.6 x 2.34
Pitch (mm): 1.27

Environmental & Export Classifications

Pb (Lead) Free Yes
Moisture Sensitivity Level (MSL) 1
ECCN (US)
HTS (US)

Product Attributes

Pkg. Type SOIC
Lead Count (#) 28
Pb (Lead) Free Yes
Carrier Type Tube
Advanced Features Spread Spectrum
C-C Jitter Max P-P (ps) 30
C-C Jitter Typ P-P (ps) 19
Core Voltage (V) 3.3
Divider Value 2, 4
Feedback Divider 250 - 511
Feedback Input No
Input Freq (MHz) 14 - 25
Input Type Crystal
Inputs (#) 1
Length (mm) 17.9
MOQ 26
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 2
Output Freq Range (MHz) 62.5 - 350
Output Signaling LVPECL
Output Type LVPECL
Output Voltage (V) 3.3
Outputs (#) 2
Package Area (mm²) 136
Pb Free Category e3 Sn
Pitch (mm) 1.27
Pkg. Dimensions (mm) 17.9 x 7.6 x 2.34
Prog. Clock Yes
Prog. Interface Parallel
Published No
Qty. per Carrier (#) 26
Qty. per Reel (#) 0
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Tape & Reel No
Temp. Range (°C) 0 to 70°C
Thickness (mm) 2.34
VCO Max Freq (MHz) 700
VCO Min Freq (MHz) 250
Width (mm) 7.6
Xtal Freq (KHz) 14 - 25
Xtal Inputs (#) 1

Description

The 8431-21 is a general purpose clock frequency synthesizer for IA64/32 application. The VCO operates at a frequency range of 250MHz to 700MHz providing an output frequency range of 62.5MHz to 350MHz. The output frequency can be programmed using the parallel interface, M0 through M8 to the configuration logic, and the output divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1. Programmable features of the 8431-21 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the 8431-21 can immediately change spread-spectrum operation without having to reset the device. In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers.