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FemtoClock Crystal-to-HCSL Clock Generator

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:DQG28
Lead Count (#):28
Pkg. Dimensions (mm):9.7 x 6.1 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)28
Carrier TypeTube
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)48
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesReference Output
App Jitter CompliancePCIe
C-C Jitter Max P-P (ps)60
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)25 - 25
Input TypeCrystal, LVCMOS
Inputs (#)2
Length (mm)9.7
MOQ48
Output Banks (#)3
Output Freq Range (MHz)25 - 25, 125 - 125, 156.25 - 156.25
Output Skew (ps)140
Output TypeHCSL, LVCMOS
Output Voltage (V)3.3
Outputs (#)5
Package Area (mm²)47
Phase Jitter Max RMS (ps)0.54
Phase Jitter Typ RMS (ps)0.41
Pitch (mm)0.65
Pkg. Dimensions (mm)9.7 x 6.1 x 1.0
Pkg. TypeTSSOP
Prog. ClockNo
PublishedNo
Reference OutputYes
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1
Width (mm)6.1

Description

The 841664I is an optimized sRIO clock generator. The device uses a 25MHz parallel crystal to generate 125MHz and 156.25MHz clock signals, replacing solution requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial application, the 841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches and bridges.