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Synchronous Ethernet WAN PLL

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)3

Product Attributes

Pkg. TypeVFQFPN
Lead Count (#)72
Pb (Lead) FreeYes
Carrier TypeReel
Country of AssemblyTAIWAN
Country of Wafer FabricationTAIWAN
Advanced FeaturesHitless Reference Switching, External Sync Input
App Jitter ComplianceStratum 3, Stratum 4, Stratum 4E, SMC, ITU, Telcordia
ApplicationSystem Synchronizer
Channels (#)1
Clock SupportG.813 Opt 1, G.813 Opt 2, G.8262 Opt 1, G.8262 Opt 2, GR-1244-CORE Stratum 4, GR-1244-CORE Stratum 4E, GR-1244-CORE Stratum 3, GR-253-CORE SONET Minimum Clock, GR-253-CORE SONET Stratum 3
Core Voltage (V)3.3
Diff. Inputs2
Diff. Outputs2
Input Freq (MHz)1.0E-6 - 625
Input Freq Range Type1PPS (1 Hz), TDM, DS1, E1, SONET/SDH, Ethernet, Sync Pulse
Input TypeAMI, LVPECL, LVDS, LVCMOS
Inputs (#)6
Length (mm)10
MOQ2500
Moisture Sensitivity Level (MSL)3
Output Banks (#)6
Output Freq Range (MHz)1.0E-6 - 644.531
Output Freq Range Type1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X
Output SignalingLVPECL, LVDS, LVCMOS, AMI
Output TypeLVPECL, LVDS, LVCMOS, AMI
Output Voltage (V)3.3
Outputs (#)8
Package Area (mm²)100
Pb Free Categorye3 Sn
Phase Jitter Typ RMS (ps)0.8
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Prog. ClockYes
Prog. InterfaceI2C, SPI
PublishedNo
Qty. per Carrier (#)0
Qty. per Reel (#)2500
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Temp. Range (°C)0 to 70°C
Thickness (mm)1
Width (mm)10

Description

The 82V3398 is an integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) for Stratum 3, 4E, 4, SMC, EECOption1, EEC-Option2 clocks in SONET/SDH/Synchronous Ethernet equipment, DWDM, and wireless base stations. The device consists of a high-quality and configurable DPLL to provide a system clock for node timing synchronization within a SONET/SDH/Synchronous Ethernet network.