Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 48 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 30.72 - 30.72 |
| Input Type | Crystal, LVPECL, LVDS, CML |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 2000 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 30.72 - 30.72, 122.88 - 122.88, 153.6 - 153.6 |
| Output Skew (ps) | 100 |
| Output Type | LVDS |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Outputs (#) | 9 |
| Package Area (mm²) | 49 |
| Period Jitter Max P-P (ps) | 4 |
| Period Jitter Typ P-P (ps) | 2.1 |
| Phase Jitter Max RMS (ps) | 0.89 |
| Phase Jitter Typ RMS (ps) | 0.642 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Product Category | FemtoClock, Low Jitter Clocks (<700 fs RMS) |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 7 |
Resources for 814S208I
Description
The 814S208I is an eight LVDS output clock synthesizer designed for wireless infrastructure applications. The device generates eight copies of a selectable 122.88MHz or 153.6MHz clock signal with excellent phase jitter performance. The PLL is optimized for a reference frequency of 30.72MHz. Both a crystal interface and a differential system clock input are supported for the reference frequency. An extra LVDS output duplicates the reference frequency and is provided for clock tree cascading. The device uses Renesas' third generation FemtoClock® technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption. A PLL lock status output is provided for monitoring and diagnosis purpose. The device supports a 3.3V voltage supply and is packaged in a small, lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.