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Jitter Attenuator & FemtoClock NG Multiplier

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG32
Lead Count (#):32
Pkg. Dimensions (mm):5.0 x 5.0 x 0.9
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)32
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Input TypeLVPECL, LVDS, HCSL, HSTL
Output Skew (ps)50
Qty. per Reel (#)2500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Abs. Pull Range Min. (± PPM)50
Advanced FeaturesVCXO-based APLL
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)0.008 - 156.25
Inputs (#)2
Length (mm)5
Loop Bandwidth Range (Hz)9 - 56
MOQ2500
Output Banks (#)2
Output Freq Range (MHz)19.44 - 622.08
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)2
Package Area (mm²)25
Phase Jitter Max RMS (ps)0.736
Phase Jitter Typ RMS (ps)0.616
Pitch (mm)0.5
Pkg. Dimensions (mm)5.0 x 5.0 x 0.9
Pkg. TypeVFQFPN
Prog. ClockNo
PublishedNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)0.9
Width (mm)5
Xtal Freq (KHz)27000 - 27000

Description

The 813N322I-02 device uses Renesas' fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 813N322I-02 is a PLL-based synchronous multiplier that is optimized for Ethernet to SONET/PDH clock jitter attenuation and frequency translation. The 813N322I-02 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provides the low jitter, high-frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.