Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 32 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Input Type | LVDS, LVPECL, LVHSTL, SSTL, HCSL |
| Output Skew (ps) | 25 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Abs. Pull Range Min. (± PPM) | 50 |
| Advanced Features | VCXO-based APLL |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 0.008 - 156.25 |
| Inputs (#) | 2 |
| Length (mm) | 5 |
| MOQ | 2500 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 19.44 - 622.08 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 25 |
| Phase Jitter Typ RMS (ps) | 0.616 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Prog. Clock | No |
| Published | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (KHz) | 27000 - 27000 |
Resources for 813N322I-02
Description
The 813N322I-02 device uses Renesas' fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 813N322I-02 is a PLL-based synchronous multiplier that is optimized for Ethernet to SONET/PDH clock jitter attenuation and frequency translation. The 813N322I-02 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provides the low jitter, high-frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.