Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 32 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Abs. Pull Range Min. (± PPM) | 50 |
| Advanced Features | VCXO-based APLL |
| Application | Port Synchronizer |
| Channels (#) | 1 |
| Core Voltage (V) | 3.3 |
| Diff. Inputs | 2 |
| Diff. Outputs | 2 |
| Feedback Input | No |
| Fractional Output Dividers (#) | 0 |
| Input Freq (MHz) | 0.008 - 155.52 |
| Input Freq Range Type | Ethernet |
| Input Type | LVPECL, LVDS, HSTL, SSTL, HCSL |
| Inputs (#) | 2 |
| Length (mm) | 5 |
| Loop Bandwidth Range (Hz) | 75 |
| MOQ | 490 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 25 - 312.5 |
| Output Freq Range Type | 100BASE-T, 1000BASE-T/X, XGMII/XAUI |
| Output Skew (ps) | 25 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 25 |
| Phase Jitter Typ RMS (ps) | 0.3 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Product Category | FemtoClock NG |
| Prog. Clock | No |
| Published | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (KHz) | 25000 - 25000 |
Resources for 813N252I-09
Description
The 813N252I-09 is a PLL-based synchronous multiplier optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high-frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.
Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper