Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PAG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 14.0 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Pkg. Type | TSSOP |
| Lead Count (#) | 56 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Bus Width (bits) | 24 |
| Core Voltage (V) | 3.3 |
| Function | Latch |
| Length (mm) | 14 |
| MOQ | 578 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Type | 3-state |
| Package Area (mm²) | 85.4 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 14.0 x 6.1 x 1.0 |
| Published | No |
| Qty. per Carrier (#) | 34 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Speed Grade | Standard |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
Resources for 74ALVCH16260
Description
The 74ALVCH16260 12-bit to 24-bit multiplexed D-type latch is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. The 74ALVCH16260 has "bus-hold" which prevents floating inputs and eliminates the need for pull-up/down resistors. The 74ALVCH16260 operates at -40C to +85C