Features
- Free-running clock lines for each port
- IDT Standard timing
- Empty and Full flag functions
- Programmable Almost-Empty and Almost-Full flags
- Bus sizing of 18-bits (word) and 9-bits (byte)
- Byte order swapping on ports B and C
- Passive parity checking on ports A and C
- Parity generation can be selected for ports A and B
- Master Reset clears data and configures FIFO
- Width can be easily expanded by adding FIFOs
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
- Industrial temperature range (–40oC to +85oC) is available
Description
The 723616 is a 64 x 36 x 2 Triple Bus SyncFIFO memory which supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.