Skip to main content
256K x 36 Async, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's

Package Information

CAD Model:View CAD Model
Pkg. Type:PQFP
Pkg. Code:DR208
Lead Count (#):208
Pkg. Dimensions (mm):28.0 x 28.0 x 3.5
Pitch (mm):0.5

Environmental & Export Classifications

Pb (Lead) FreeNo
Moisture Sensitivity Level (MSL)3
ECCN (US)
HTS (US)

Product Attributes

Lead Count (#)208
Pb (Lead) FreeNo
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Access Time (ns)10
ArchitectureDual-Port
Bus Width (bits)36
Core Voltage (V)2.5
Density (Kb)9216
FunctionBusy, Interrupt, JTAG, Master, Semaphore, Slave, Sleep Mode
I/O Type2.5 V LVTTL, 3.3 V LVTTL
InterfaceAsync
Length (mm)28
MOQ12
Organization256K x 36
Package Area (mm²)784
Pb Free Categorye0
Pitch (mm)0.5
Pkg. Dimensions (mm)28.0 x 28.0 x 3.5
Pkg. TypePQFP
PublishedNo
Qty. per Carrier (#)24
Qty. per Reel (#)0
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Temp. Range (°C)0 to 70°C
Thickness (mm)3.5
Width (mm)28

Description

The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.