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Low Phase Noise Clock Multiplier

Package Information

CAD Model:View CAD Model
Pkg. Type:SOIC
Pkg. Code:DCG16
Lead Count (#):16
Pkg. Dimensions (mm):9.9 x 3.9 x 1.5
Pitch (mm):1.27

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)3
Qty. per Carrier (#)48
Package Area (mm²)38.6
Pitch (mm)1.27
Pkg. Dimensions (mm)9.9 x 3.9 x 1.5
Qty. per Reel (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Accepts Spread Spec InputYes
Advanced FeaturesAccepts Spread Spec Input, Reference Output
C-C Jitter Max P-P (ps)18
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)10 - 27
Input TypeCrystal, LVCMOS
Inputs (#)5
Length (mm)9.9
MOQ192
Output Banks (#)2
Output Freq Range (MHz)156
Output Skew (ps)250
Output TypeLVCMOS
Output Voltage (V)3.3V, 5V
Outputs (#)2
Period Jitter Max P-P (ps)75
Period Jitter Typ P-P (ps)50
Pkg. TypeSOIC
Prog. ClockNo
PublishedNo
Reference OutputYes
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Supply Voltage (V)3.3 - 5
Tape & ReelNo
Thickness (mm)1.5
Width (mm)3.9
Xtal Freq (KHz)10 - 27
Xtal Inputs (#)1

Description

The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is Renesas’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using Renesas’ patented analog and digital Phase-Locked Loop (PLL)  techniques, the chip accepts a 10 - 27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS670-01.