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EEPROM Programmable VCXO Clock Generator

Package Information

CAD Model: View CAD Model
Pkg. Type: VFQFPN
Pkg. Code: NDG28
Lead Count (#): 28
Pkg. Dimensions (mm): 4.0 x 4.0 x 0.9
Pitch (mm): 0.4

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090
Moisture Sensitivity Level (MSL) 1

Product Attributes

Pkg. Type VFQFPN
Lead Count (#) 28
Pb (Lead) Free Yes
Carrier Type Reel
Advanced Features Programmable Clock, Spread Spectrum, Reference Output
Core Voltage (V) 3.3
Family Name VersaClock 3
Input Freq (MHz) 1 - 200
Input Type Crystal, LVCMOS
Inputs (#) 2
Length (mm) 4
MOQ 2500
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 5
Output Freq Range (MHz) 0.001 - 200
Output Skew (ps) 75
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 5
Package Area (mm²) 16
Pb Free Category e3 Sn
Period Jitter Max P-P (ps) 100
Period Jitter Typ P-P (ps) 80
Pitch (mm) 0.4
Pkg. Dimensions (mm) 4.0 x 4.0 x 0.9
Prog. Clock Yes
Prog. Interface I2C, EEPROM
Published No
Qty. per Carrier (#) 0
Qty. per Reel (#) 2500
Reel Size (in) 13
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Tape & Reel Yes
Temp. Range (°C) -40 to 85°C
Thickness (mm) 0.9
Width (mm) 4

Description

The 5V19EE603 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V19EE603 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of five 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.