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Precision Clock Generator

Package Information

Pkg. Type: VFQFPN
Pkg. Code: NLG28
Lead Count (#): 28
Pkg. Dimensions (mm): 6.0 x 6.0 x 0.85
Pitch (mm): 0.65

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090
Moisture Sensitivity Level (MSL) 3

Product Attributes

Pkg. Type VFQFPN
Lead Count (#) 28
Pb (Lead) Free Yes
Carrier Type Tray
Core Voltage (V) 3.3V, 2.5V
Feedback Input No
Input Freq (MHz) 667 - 667
Input Type LVPECL, LVDS, LVTTL
Inputs (#) 2
Length (mm) 6
MOQ 35
Moisture Sensitivity Level (MSL) 3
Output Banks (#) 2
Output Freq Range (MHz) 666.52 - 666.52
Output Signaling LVDS
Output Skew (ps) 20
Output Type LVDS
Output Voltage (V) 3.3V, 2.5V
Outputs (#) 2
Package Area (mm²) 36
Pb Free Category e3 Sn
Phase Jitter Max RMS (ps) 0.3
Phase Jitter Typ RMS (ps) 0.65
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.0 x 6.0 x 0.85
Prog. Clock No
Published No
Qty. per Carrier (#) 490
Qty. per Reel (#) 0
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Tape & Reel No
Temp. Range (°C) -40 to 85°C
Thickness (mm) 0.85
Width (mm) 6

Description

The 5T940 generates a high precision FEC (Forward Error Correction)or non-FEC source clock for SONET/SDH systems as well as a source clock for Gigabit Ethernet systems. This device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. In the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. This device detects loss of valid CLKIN and leaves the VCO of the PLL at the last valid frequency while an alternate input REFIN is selected. If CLKIN and REFIN are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. The 5T940 can act as a translator from a differential LVPECL, LVDS, or single-ended LVTTL input to LVPECL or LVDS outputs. The 5T940-10 has LVDS outputs and the 5T940-30 has LVPECL outputs. The three modes of output frequency range are controlled by the SELmode, which is a 3-level pin. When SELmode is high or low, the QOUT is a multiplied version of the input clock while QREG is a regenerated version of the input clock. When SELmode is mid, the QOUT is a multiplied version of the input clock while QREG is QOUT/4.The 5T940 features a selectable loop bandwidth. The 5T940 features a selectable loop bandwidth.