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2.5V LVDS,1:2 Clock Buffer Terabuffer™

Package Information

CAD Model: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: EJG20
Lead Count (#): 20
Pkg. Dimensions (mm): 6.6 x 4.4 x 1.0
Pitch (mm): 0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Pkg. Type TSSOP
Lead Count (#) 20
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2500
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Core Voltage (V) 2.5
Function Buffer, Multiplexer
Input Freq (MHz) 450
Input Type CML, HSTL, LVDS, LVCMOS, LVPECL
Inputs (#) 2
Length (mm) 6.6
MOQ 2500
Output Banks (#) 1
Output Freq Range (MHz) 450
Output Skew (ps) 50
Output Type LVDS
Output Voltage (V) 2.5
Outputs (#) 2
Package Area (mm²) 29
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.6 x 4.4 x 1.0
Published No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4

Description

The 5T9302 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9302 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9302 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.