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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.

2.5V Single Data Rate 1:10 Clock Buffer Terabuffer™

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PAG48
Lead Count (#):48
Pkg. Dimensions (mm):12.5 x 6.1 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)48
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Core Voltage (V)2.5
Input TypeHSTL, LVTTL, LVCMOS, LVPECL
Output Skew (ps)25
Output Voltage (V)2.5V, 1.8V, 1.5V
Qty. per Reel (#)2000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Input Freq (MHz)250
Inputs (#)1
Length (mm)12.5
MOQ2000
Output Banks (#)2
Output Freq Range (MHz)250
Output SignalingLVCMOS
Output TypeLVCMOS
Outputs (#)10
Package Area (mm²)76.3
Pitch (mm)0.5
Pkg. Dimensions (mm)12.5 x 6.1 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1
Width (mm)6.1

Description

The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T907 has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.