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Renesas Electronics Corporation
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer™

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG28
Lead Count (#):28
Pkg. Dimensions (mm):9.7 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)28
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Input TypeLVCMOS
Output Skew (ps)60
Output Voltage (V)2.5
Qty. per Reel (#)0
Qty. per Carrier (#)50
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Core Voltage (V)2.5
FunctionBuffer
Input Freq (MHz)250
Inputs (#)1
Length (mm)9.7
MOQ100
Output Banks (#)1
Output Freq Range (MHz)250
Output TypeLVCMOS
Outputs (#)5
Package Area (mm²)42.7
Pitch (mm)0.65
Pkg. Dimensions (mm)9.7 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The 5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.