| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN, MALAYSIA |
| Country of Wafer Fabrication | SINGAPORE |
| Additive Phase Jitter Typ P-P (fs) | 0.5 |
| Advanced Features | Programmable Clock, Reference Output, Spread Spectrum |
| C-C Jitter Typ P-P (ps) | 46 |
| Core Voltage (V) | 1.8V, 2.5V, 3.3V |
| Family Name | VersaClock 6 |
| Input Freq (MHz) | 1 - 350 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, HCSL |
| Inputs (#) | 2 |
| Length (mm) | 4 |
| MOQ | 490 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 1 - 350 |
| Output Skew (ps) | 75 |
| Output Type | LVCMOS, LVPECL, HCSL, LVDS |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Outputs (#) | 3 |
| Package Area (mm²) | 16 |
| Phase Jitter Typ RMS (fs) | 500 |
| Phase Jitter Typ RMS (ps) | 0.5 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Price (USD) | $4.71061 |
| Prog. Clock | Yes |
| Prog. Interface | I2C, OTP |
| Published | No |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 4 |
| Xtal Freq (MHz) | 8 - 40 |
| Xtal Inputs (#) | 1 |
The 5P49V6913 is a programmable clock generator intended for high-performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using the I²C interface. This is Renesas' sixth generation of programmable clock technology (VersaClock® 6). The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.
Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power down), regional standards (US, Japan, Europe), or system production margin testing. The device may be configured to use one of two I²C addresses to allow multiple devices to be used in a system.